FlipFlop - Examn f(CLK)

General Discussions
#1

Guys, i have a question from a Brasilian computer examn and im trying to solve and it seems to be really simple but i lack the knowledge on flip flops…
Anyone have tips to help solve this?

I will post the translated question and link.
http://www.cops.uel.br/concursos/153_poscomp_2013/15301_DEF.PDF

The following picture shows a assync counter acting as a frequency divider.The clock frequency is (fCLK) 60 Hz.
Considering the inputs J and K from all Flip-flops which are permanently in high logic level, the frequency signal from Q3 Exit will be?
a) 05 Hz.
b) 06 Hz.
c) 12 Hz.
d) 15 Hz.
e) 16 Hz.

Im a bit desperate , so any help will be great.

[quote]A figura, a seguir, mostra um contador assíncrono atuando como um divisor de frequência, cuja frequência
de relógio (fCLK) é de 60 Hz.
Considerando que as entradas J e K de todos os flip-flops estão permanentemente em nível lógico alto, a
frequência do sinal na saída Q3 será de
a) 05 Hz.
b) 06 Hz.
c) 12 Hz.
d) 15 Hz.
e) 16 Hz.
[/quote]
Obs : I sorry if this is the wrong place to post but i know that in this forum we have a lot of people with different knowledge in different areas and so i think you might be able to help me out.

#2

JK Flip Flops:

if J and K are both 0, then theres no change.
if J = 0 K = 1, its a reset
if J = 1 K = 0, it is a set
if J = 1 and K = 1, it toggles (light a light switch, if its on, then it becomes off, if its off then it becomes on).

so were using toggle always.

its starts at 60 Hz, then it gets ouputted as 0, it goes in the second JK flip flop, and becomes 5 (very badly written question, it makes you assume you know the voltage that is supplied). the third JK flip flop makes it a 0, and the fourth returns it to be ouputted as 5.

therefor the answer to the question is 5 Hz.

How the answer is 5 Hz, well I cant read your exam, so I cant tell if it says what the voltage supplied to all circuits is, or if you got taught to always use a certain voltage.

EDIT: If I had to answer the question as non multiple choice, I would of probably wrote 60 Hz.

#3

THANK YOU SO MUCH!!
its starts at 60 Hz, then it gets ouputted as 0, it goes in the second JK flip flop, and becomes 5 (very badly written question, it makes you assume you know the voltage that is supplied)

But why it gets outputted to 0 and then to 5?

#4

like I said it is badly written.

The output should be what the input theres no answer for 60Hz.

so I assume default high in that circuit is 5 Hz. so a high in the circuit is 5, and a low is 0.

on the outputs of each of the JK flip flops will be

JK (1) = low (toggled from a high to output a low)
JK (2) = high (toggled from a low to output a high)
JK (3) = low (toggled from a high to output a low)
JK (4) = high (toggled from a low to output a high)

as the output just toggles between high and low, because when both J and K are high, it makes a toggle.

by the answer, I am assuming high = 5Hz, and low = 0hz.

JK (1) = 0hz
JK (2) = 5hz
JK (3) = 0hz
JK (4) = 5hz

You shouldn’t be sitting an exam you know nothing about. circuits can get complicated very fast, especially when you start using flip flops. But if you know the theory behind it, it is a very easy class (at least at my uni).

#5

I’m a little bit rusty, and don’t know entirely what the question is asking, but since it is a frequency divider, then the frequency will halve after each flip-flop.

So you have 3 flips-flops, the frequency should be 15/2Hz shouldn’t it?

Clock (60Hz) -> JK -> Q (30Hz) ->JK -> Q (15Hz) -> JK -> (15/2Hz)

Maybe its something like an off by one that I don’t know about, so you only have to flip-flops. In that case, it would be 15 Hz.

Phased: You’re thinking of voltage :wink:

#6

Im not good with circuits, i like graphs, programming and love LOVE calculus.

But circuits always give me head ache.
Thanks a lot.

I will print and read in the morning.

The examn have other questions as well.
Will be next sunday!!

#7

Longarmx: By the answer, you are still wrong though, as the answer is 5Hz (marked by red).

also there is 4 JK flip flops, so the answer would be 7.5Hz (by your definition).

We never really had a question like this, we answered if the output was high or low, or a timing diagram.

#8

Yep, I just looked at the question. So it should be 3.75Hz (60 / 2^4), but maybe they just rounded up??

#9

I dont think so.
I think there must be some definition we are missing

#10

I believe it would be 5 defined by a high = 5Hz and low = 0hz,

where 60Hz is a high, so it starts high, goes low, goes high, goes low and finishes on the last flip flop as a high.

now work out what the value of a high is.

By what a flip flop does, at J = 1 and K = 1, the value is flipped between high and low.

Also, i just worked out the answer.

the clock is 60 Hz (non required information).

we have 2 possible answers, if we start at a low, we will end with a low, if we start with a high we will end with a high.

No answers are low ( 0 Hz), so it starts as a high, and finished with a high.

at no point does it say what a high is (at least not in english).

One of the standard is like 0 hz and 5hz i think, so, high = 5 Hz, and low = 0Hz.

possible answers are

0hz (starting as a low)

5Hz (starting as a high)

#11

High would be 5V, low is 0V. This is frequency.

Also, high and low can reverse whether you’re talking about common anode or common cathode.

#12

the clock is not required, as the clock only means how often it is executed, in this case it is a falling edge executed, and by the little timing diagram, is it executed straight away.

there for the JK flip flops are currently active.

#13

Pretty sure this is just crappy test question style writing: Pick the closest answer, not the exact answer. Hence 5 Hz as the actual output is 3.75 Hz as figured by Longarmx.

EDIT: unless it’s way trickier than I’d say is warranted on such a test and I’m not remembering how/if the CLR bus affects the frequency… if anything I’d think something like (f1-1 + f2-1)-1 which still isn’t 5…

#14

we never did questions like this, so I tried to adapt questions that we did to this.

From google searching you are right. its Frequency division. which we never learnt about.

So sorry Longarmx, but I think this full theory could also help Andre Lopes, in the understanding of how JK Flip Flops work.

so the correct answer is actually 3.75 Hz. (which from my little research only works for toggle flip flops I believe? (where a JK flip flop with J and K both are 1 is a toggle) )

and all my replies is on how Toggle works in a JK Flip Flop.

#15

Playing with it here, interesting thing is the output of the NAND is 3.75/3 = 1.25 Hz (although a weird non-symmetrical duty cycle), but the built in JK flops don’t have a clear so I can’t determine what affect that has. There is a JK flop from scratch in the examples if you want to try it yourself.

#16

3.75 ( from flip flops ) + 1.25 of NAND = 5

Is that it?

#17

It’s asking for the output from Q3, so the NAND shouldn’t affect it. The NAND is just there to reset all the flip-flops.

#18

https://fbcdn-sphotos-d-a.akamaihd.net/hphotos-ak-xap1/t31.0-8/10608616_725510044163477_2253453777023079711_o.jpg

Please, can Anyone can explain this to me?

#19

Since the NAND will trigger the clear whenever Q3 and Q2 become 1, the last 4 truth table conditions will never happen. Thus, you only have 12 possible states of the flip-flops. This shouldn’t affect the frequency though…

#20

Think about it. The NAND resets all flip flops every twelve ticks. The question is asking about the output of Q3. There is only one low->high flip for Q3 at the 9th tick (on that paper) …

Now again - this does not??? affect the frequency of Q3 - really, come on… :stuck_out_tongue: